1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly to a device structure that achieves a high performance by fine patterning of a device region in a semiconductor integrated circuit using an SOI substrate.
2. Description of the Related Art
In recent years, as regards an LSI that is formed on a silicon substrate, a remarkable increase in performance is achieved by fine patterning of devices that are employed. This is because an improvement in performance of logic circuits or MOSFETs used in a memory device such as an SRAM is achieved by shrinkage in gate length or reduction in thickness of a gate insulation film according to so-called scaling rules. A further important point is that a short channel effect is suppressed by decreasing the junction depth in the source/drain regions.
To meet these requirements, there is an attempt to form a MOSFET on an SOI, thereby constituting an LSI. MOSFETs to be formed on the SOI fall into two kinds of devices: a partially depleted (PD) MOSFET and a fully depleted (FD) MOSFET. It is thought that in a future generation in which shallow junctions are required, the FD MOSFET that includes a thinner silicon layer will be more advantageous.
However, it is known that the FD-SOIMOSFET has the following drawbacks:
(1) The FD-SOIMOSFET is susceptible to a short channel effect, and reduction in thickness of the silicon layer is required in order to prevent such a short channel effect.
(2) The threshold cannot be freely controlled since the concentration in the substrate is such a low level that the channel is fully depleted.
(3) A parasitic resistance tends to increase.
As regards these drawbacks, a conventional FD-SOIMOSFET, in principle, is able to control the threshold only by two factors: a work function of a gate electrode, and the thickness of a silicon layer (i.e. at which voltage a depletion layer completely extends and a fully depleted channel is formed).
There are proposed some methods for controlling the threshold, which include adoption of a double-gate structure wherein a thin channel region is vertically sandwiched between gate electrodes and equal potentials are applied to the channel region at a time to control the potential of the channel, and adoption of a back-gate structure wherein one-side voltage is fixed and used to adjust the threshold.
However, the above-mentioned structures, which have been reported so far, are very complicated and difficult to fabricate. There is a demand for a device architecture that is simple and easy to fabricate. In particular, in an LSI, it is not possible to provide a MOSFET that simply has a single threshold (Vt). It is necessary to realize multi-Vt (plural threshold voltages) within the circuit, but it is not easy to realize multi-Vt in a conventional structure if an LSI is to be constituted using an FD-SOI. A structure, where a support substrate is uniformly doped and a potential is applied, is disclosed in T. Ohtou et al.: Extended Abstract of International Conference on Solid State Devices and Materials (SSDM 2003), pp. 272-273 (2003). This structure, however, is unable to control the threshold of an arbitrary device, and is susceptible to latch-up.
It is also proposed in T. Yamada et al.: Symp. On VLSI Tech 2002, pp. 112-113 that after an SOI portion and a BOX film is partly removed and a silicon region is epitaxially grown on a support substrate, a MOSFET is formed on the silicon region to provide a device including an SOIMOSFET and a bulk MOSFET.
FIG. 10 is a cross-sectional view taken in a direction perpendicular to the channel direction of a prior-art FD-SOIMOSFET 90. For simple depiction, contacts and subsequently formed metal wiring layers are not shown. The MOSFET 90 comprises a support substrate 91, a silicon region 92 of a very thin film (˜10 nm), a relatively thick buried insulation film (BOX film, ˜150 nm) 93, and a gate electrode 94.
If a back-gate structure is to be realized, a substrate bias voltage is applied to the support substrate 91. However, since the BOX film 93 has a large thickness of 150 nm, a voltage of 10V or more needs to be applied in order to cause a sufficient voltage variation. Furthermore, since an equal voltage is applied to the entire support substrate, it is not possible to locally control the threshold.
In any case, as mentioned above, it is not easy to control the threshold in the conventional FD-SOI device, and it is difficult to provide a multi-Vt structure.